1. Field of the Invention
The present invention relates to a semiconductor device including memory cells and a peripheral circuit and/or a logic circuit of a DRAM (dynamic random access memory), and a manufacturing method of the semiconductor device.
Priority is claimed on Japanese Patent Application No. 2007-090099, filed Mar. 30, 2007, the contents of which are incorporated herein by reference.
2. Description of the Related Art
Conventional semiconductor devices include general DRAMs, embedded DRAMs, and the like. In a peripheral circuit area of a general DRAM or a logic circuit area of an embedded DRAM, in order to make transistors conductive to each other, (i) first-layer wiring lines formed on the same layer as that on which a bit wiring line of a memory cell is provided below a capacitor, and (ii) second-layer wiring lines and third-layer wiring lines, which are provided above the capacitor, are electrically connected so as to form a circuit.
FIG. 16 is a general sectional view of a semiconductor device, which the inventors of the present invention have developed and studied. In the semiconductor device, a memory cell area 100 and a peripheral circuit area 101 of a DRAM cell are formed on a single semiconductor substrate 102. In the following explanations of the present specification, a peripheral circuit area of a general DRAM and a logic circuit area of an embedded DRAM are each generally called a “peripheral circuit area”.
In the memory cell area 100 of the above-described semiconductor device, diffusion layer areas 105, 106, and 107 are formed side by side, in an area interposed between element-separating insulating films 103. Between the diffusion layer areas 105 and 106, and also between the diffusion layer areas 106 and 107, a gate insulating film 108 is individually formed on the semiconductor substrate 102, and a gate electrode 109 is formed on each gate insulating film 108. Each gate electrode 109 is covered with a side-wall insulating film 110 and a separating insulating film 111, so that each gate electrode 109 is isolated in an insulated manner. These elements are covered with a first inter-layer insulating film 112, and first contact plugs 113 pass through the first inter-layer insulating film 112 in the vertical direction, so that they are individually connected to the diffusion layer areas 105, 106, and 107. A second inter-layer insulating film 115 is formed on the first inter-layer insulating film 112, and second contact plugs 116 pass through the second inter-layer insulating film in the vertical direction, so that they are individually connected to the first contact plugs 113 which are connected to the diffusion layer areas 105 and 107. In addition, a bit wiring line 117 is connected to the first contact plug 113 which is connected to (i) the diffusion layer area 106 and (ii) a part of the first inter-layer insulating film 112, from thereabove.
A third inter-layer insulating film 120 is further stacked on the second inter-layer insulating film 115, and a capacitor structure 121 is provided in the third inter-layer insulating film 120 so that it is arranged on the second contact plugs 116. The capacitor structure 121 includes lower electrodes 122, a capacitance insulating film 123, and an upper electrode 125, and is electrically connected to the second contact plugs 116 via landing pads 126, which are provided on the bottom side of the lower electrodes 122.
On the other hand, in the peripheral circuit area 101 (or a logic circuit area of an embedded DRAM), diffusion layer areas 130 and 131 are formed side by side, in an area interposed between the element-separating insulating films 103. Between the diffusion layer areas 130 and 131, a gate insulating film 132 is formed on the semiconductor substrate 102, and a gate electrode 133 is formed on the gate insulating film 132. The gate electrode 133 is covered with a side-wall insulating film 135 and a separating insulating film 136, so that the gate electrode 133 is isolated in an insulated manner. These elements are covered with the first inter-layer insulating film 112, and third contact plugs 137 pass through the first inter-layer insulating film 112 in the vertical direction, so that they are individually connected to the diffusion layer areas 130 and 131. In addition, fourth contact plugs 138A and 138B are formed in a manner such that they pass through the second inter-layer insulating film 115 and the third inter-layer insulating film 120 which are stacked on the first inter-layer insulating film 112. The fourth contact plugs 138A and 138B are respectively connected via first-layer wiring lines 139A and 139B to the third contact plugs 137, which are connected to the diffusion layer areas 130 and 131. The fourth contact plugs 138A and 138B are also connected to second wiring lines 140 which are formed on the third inter-layer insulating film 120.
In the above-described semiconductor device, the diffusion layer areas 130 and 131 each function as the source or drain area of a transistor in the peripheral circuit area 101, and the second wiring lines 140 are provided on the third inter-layer insulating film 120 which is positioned above the diffusion layer areas 130 and 131. The connection between the diffusion layer areas 130 and 131 and the second wiring lines 140 are established by means of the contact plugs 138A and 138B, which are made of metal, and formed via the first-layer wiring lines 139A and 139B in a manner such that the contact plugs 138A and 138B are embedded in the contact holes formed through the relevant inter-layer insulating films.
In a known example of such a semiconductor device which includes (i) transistor and capacitor structures in a memory cell area and (ii) transistor and wiring structures in a peripheral circuit area, and has a multilayered structure, first and second inter-layer insulating films are stacked on a semiconductor substrate, where plug electrodes pass through the inter-layer insulating films, and an aluminium wiring layer is provided via a pad layer on each plug electrode (see Japanese Unexamined Patent Application, First Publication No. H07-142597).
In another known example of such a semiconductor device, when forming a layered structure of the lower electrode of a capacitor, a power supply layer is provided at the same layer position as that of the layer of the lower electrode (see Japanese Unexamined Patent Application, First Publication No. H09-275193).
In another known example, either of the upper electrode, a dielectric film, and the lower electrode, which form a capacitor of a cell array, can be used as a local wiring line in a peripheral circuit area (see Japanese Unexamined Patent Application, First Publication No. 2000-58771).
In addition, Japanese Unexamined Patent Application, First Publication No. 2002-319632 discloses a storage node pad in a logic circuit area, which is formed through the same process as that for forming the lower electrode of a capacitor in a DRAM part (see Japanese Unexamined Patent Application, First Publication No. 2002-319632).
In a highly-integrated semiconductor device, the first-layer wiring lines 139A and 139B have a fine structure so as to provide a large number of conductive terminals with respect to the relevant transistors. Therefore, if the integration of the semiconductor device further proceeds and the layout size (i.e., F value) is decreased, fine processing of the first-layer wiring lines 139A and 139B becomes more difficult. With respect to the peripheral circuit area of a general DRAM or the logic circuit area of an embedded DRAM, wiring lines are closely arranged especially in a boundary area which is formed over the memory cell area 100 and the peripheral circuit area 101. Therefore, in such an area, finer processing of the first-layer wiring lines 139A and 139B is difficult. Additionally, accompanied with a further decrease in the wiring width, an RC delay appears. Accordingly, it is required to form the peripheral circuit or the logic circuit without further fining the first-layer wiring lines 139A and 139B.